update to glibc-2.28-151.el8.src.rpm
Signed-off-by: Liwei Ge <geliwei@openanolis.org>
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Liwei Ge
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ba6a26df65
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37da1d0798
284 changed files with 62546 additions and 13 deletions
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glibc-rh1783303-4.patch
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glibc-rh1783303-4.patch
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commit 3db85a9814784a74536a1f0e7b7ddbfef7dc84bb
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Author: Paul A. Clarke <pc@us.ibm.com>
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Date: Thu Jun 20 11:57:18 2019 -0500
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powerpc: Use faster means to access FPSCR when possible in some cases
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Using 'mffs' instruction to read the Floating Point Status Control Register
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(FPSCR) can force a processor flush in some cases, with undesirable
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performance impact. If the values of the bits in the FPSCR which force the
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flush are not needed, an instruction that is new to POWER9 (ISA version 3.0),
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'mffsl' can be used instead.
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Cases included: get_rounding_mode, fegetround, fegetmode, fegetexcept.
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* sysdeps/powerpc/bits/fenvinline.h (__fegetround): Use
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__fegetround_ISA300() or __fegetround_ISA2() as appropriate.
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(__fegetround_ISA300) New.
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(__fegetround_ISA2) New.
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* sysdeps/powerpc/fpu_control.h (IS_ISA300): New.
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(_FPU_MFFS): Move implementation...
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(_FPU_GETCW): Here.
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(_FPU_MFFSL): Move implementation....
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(_FPU_GET_RC_ISA300): Here. New.
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(_FPU_GET_RC): Use _FPU_GET_RC_ISA300() or _FPU_GETCW() as appropriate.
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* sysdeps/powerpc/fpu/fenv_libc.h (fegetenv_status_ISA300): New.
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(fegetenv_status): New.
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* sysdeps/powerpc/fpu/fegetmode.c (fegetmode): Use fegetenv_status()
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instead of fegetenv_register().
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* sysdeps/powerpc/fpu/fegetexcept.c (__fegetexcept): Likewise.
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Reviewed-by: Tulio Magno Quites Machado Filho <tuliom@linux.ibm.com>
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diff --git a/sysdeps/powerpc/bits/fenvinline.h b/sysdeps/powerpc/bits/fenvinline.h
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index 41316386ba75e903..caec8ead6e17219d 100644
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--- a/sysdeps/powerpc/bits/fenvinline.h
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+++ b/sysdeps/powerpc/bits/fenvinline.h
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@@ -18,13 +18,36 @@
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#if defined __GNUC__ && !defined _SOFT_FLOAT && !defined __NO_FPRS__
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-/* Inline definition for fegetround. */
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-# define __fegetround() \
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- (__extension__ ({ int __fegetround_result; \
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- __asm__ __volatile__ \
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- ("mcrfs 7,7 ; mfcr %0" \
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- : "=r"(__fegetround_result) : : "cr7"); \
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- __fegetround_result & 3; }))
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+/* Inline definitions for fegetround. */
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+# define __fegetround_ISA300() \
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+ (__extension__ ({ \
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+ union { double __d; unsigned long long __ll; } __u; \
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+ __asm__ __volatile__ ( \
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+ ".machine push; .machine \"power9\"; mffsl %0; .machine pop" \
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+ : "=f" (__u.__d)); \
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+ __u.__ll & 0x0000000000000003LL; \
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+ }))
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+
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+# define __fegetround_ISA2() \
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+ (__extension__ ({ \
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+ int __fegetround_result; \
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+ __asm__ __volatile__ ("mcrfs 7,7 ; mfcr %0" \
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+ : "=r"(__fegetround_result) : : "cr7"); \
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+ __fegetround_result & 3; \
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+ }))
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+
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+# ifdef _ARCH_PWR9
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+# define __fegetround() __fegetround_ISA300()
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+# elif defined __BUILTIN_CPU_SUPPORTS__
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+# define __fegetround() \
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+ (__glibc_likely (__builtin_cpu_supports ("arch_3_00")) \
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+ ? __fegetround_ISA300() \
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+ : __fegetround_ISA2() \
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+ )
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+# else
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+# define __fegetround() __fegetround_ISA2()
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+# endif
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+
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# define fegetround() __fegetround ()
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# ifndef __NO_MATH_INLINES
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diff --git a/sysdeps/powerpc/fpu/fegetexcept.c b/sysdeps/powerpc/fpu/fegetexcept.c
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index a053a32bfe11c0d4..9d77adea59939ece 100644
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--- a/sysdeps/powerpc/fpu/fegetexcept.c
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+++ b/sysdeps/powerpc/fpu/fegetexcept.c
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@@ -25,7 +25,7 @@ __fegetexcept (void)
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fenv_union_t fe;
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int result = 0;
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- fe.fenv = fegetenv_register ();
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+ fe.fenv = fegetenv_status ();
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if (fe.l & (1 << (31 - FPSCR_XE)))
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result |= FE_INEXACT;
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diff --git a/sysdeps/powerpc/fpu/fegetmode.c b/sysdeps/powerpc/fpu/fegetmode.c
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index b83dc9f625d2248a..75493e5f24c8b05b 100644
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--- a/sysdeps/powerpc/fpu/fegetmode.c
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+++ b/sysdeps/powerpc/fpu/fegetmode.c
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@@ -21,6 +21,6 @@
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int
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fegetmode (femode_t *modep)
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{
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- *modep = fegetenv_register ();
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+ *modep = fegetenv_status ();
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return 0;
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}
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diff --git a/sysdeps/powerpc/fpu/fenv_libc.h b/sysdeps/powerpc/fpu/fenv_libc.h
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index d6945903b525748e..cc00df033da47c1a 100644
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--- a/sysdeps/powerpc/fpu/fenv_libc.h
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+++ b/sysdeps/powerpc/fpu/fenv_libc.h
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@@ -35,6 +35,27 @@ extern const fenv_t *__fe_mask_env (void) attribute_hidden;
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#define fegetenv_register() \
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({ fenv_t env; asm volatile ("mffs %0" : "=f" (env)); env; })
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+/* Equivalent to fegetenv_register, but only returns bits for
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+ status, exception enables, and mode. */
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+
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+#define fegetenv_status_ISA300() \
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+ ({register double __fr; \
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+ __asm__ __volatile__ ( \
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+ ".machine push; .machine \"power9\"; mffsl %0; .machine pop" \
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+ : "=f" (__fr)); \
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+ __fr; \
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+ })
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+
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+#ifdef _ARCH_PWR9
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+# define fegetenv_status() fegetenv_status_ISA300()
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+#else
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+# define fegetenv_status() \
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+ (__glibc_likely (__builtin_cpu_supports ("arch_3_00")) \
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+ ? fegetenv_status_ISA300() \
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+ : fegetenv_register() \
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+ )
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+#endif
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+
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/* Equivalent to fesetenv, but takes a fenv_t instead of a pointer. */
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#define fesetenv_register(env) \
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do { \
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diff --git a/sysdeps/powerpc/fpu_control.h b/sysdeps/powerpc/fpu_control.h
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index 90063d77bbbf794f..e0ee622e246c0d61 100644
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--- a/sysdeps/powerpc/fpu_control.h
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+++ b/sysdeps/powerpc/fpu_control.h
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@@ -96,35 +96,37 @@ extern fpu_control_t __fpu_control;
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typedef unsigned int fpu_control_t;
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/* Macros for accessing the hardware control word. */
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-# define __FPU_MFFS() \
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- ({register double __fr; \
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- __asm__ __volatile__("mffs %0" : "=f" (__fr)); \
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- __fr; \
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- })
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-
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# define _FPU_GETCW(cw) \
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({union { double __d; unsigned long long __ll; } __u; \
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- __u.__d = __FPU_MFFS(); \
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+ __asm__ __volatile__("mffs %0" : "=f" (__u.__d)); \
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(cw) = (fpu_control_t) __u.__ll; \
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(fpu_control_t) __u.__ll; \
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})
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-#ifdef _ARCH_PWR9
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-# define __FPU_MFFSL() \
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- ({register double __fr; \
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- __asm__ __volatile__("mffsl %0" : "=f" (__fr)); \
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- __fr; \
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+# define _FPU_GET_RC_ISA300() \
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+ ({union { double __d; unsigned long long __ll; } __u; \
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+ __asm__ __volatile__( \
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+ ".machine push; .machine \"power9\"; mffsl %0; .machine pop" \
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+ : "=f" (__u.__d)); \
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+ (fpu_control_t) (__u.__ll & _FPU_MASK_RC); \
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})
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-#else
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-# define __FPU_MFFSL() __FPU_MFFS()
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-#endif
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-
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-# define _FPU_GET_RC() \
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- ({union { double __d; unsigned long long __ll; } __u; \
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- __u.__d = __FPU_MFFSL(); \
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- __u.__ll &= _FPU_MASK_RC; \
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- (fpu_control_t) __u.__ll; \
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+
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+# ifdef _ARCH_PWR9
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+# define _FPU_GET_RC() _FPU_GET_RC_ISA300()
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+# elif defined __BUILTIN_CPU_SUPPORTS__
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+# define _FPU_GET_RC() \
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+ ({fpu_control_t __rc; \
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+ __rc = __glibc_likely (__builtin_cpu_supports ("arch_3_00")) \
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+ ? _FPU_GET_RC_ISA300 () \
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+ : _FPU_GETCW (__rc) & _FPU_MASK_RC; \
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+ __rc; \
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+ })
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+# else
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+# define _FPU_GET_RC() \
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+ ({fpu_control_t __rc = _FPU_GETCW (__rc) & _FPU_MASK_RC; \
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+ __rc; \
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})
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+# endif
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# define _FPU_SETCW(cw) \
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{ union { double __d; unsigned long long __ll; } __u; \
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