import glibc-2.28-101.el8.src.rpm
Signed-off-by: zhangbinchen <zhangbinchen@openanolis.org>
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zhangbinchen
commit
ba6a26df65
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273
power6emul.c
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273
power6emul.c
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/* Emulate power6 mf[tf]gpr and fri[zpmn] instructions.
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Copyright (C) 2006 Red Hat, Inc.
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Contributed by Jakub Jelinek <jakub@redhat.com>, 2006.
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This library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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It is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with the GNU C Library; if not, write to the Free
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Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
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02111-1307 USA. */
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#include <signal.h>
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#include <stdio.h>
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extern double frip (double), friz (double), frin (double), frim (double);
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asm (".globl frip, friz, frin, frim\n.hidden frip, friz, frin, frim\n\t"
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#ifdef __powerpc64__
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".section \".toc\",\"aw\"\n"
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"8:" ".tc FD_43300000_0[TC],0x4330000000000000\n"
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"9:" ".tc FD_3fe00000_0[TC],0x3fe0000000000000\n\t"
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".previous\n\t"
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#else
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".rodata\n\t"
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".align 2\n"
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"8:" ".long 0x59800000\n"
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"9:" ".long 0x3f000000\n\t"
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".previous\n\t"
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#endif
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"# frip == ceil\n"
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"frip:" "mffs 11\n\t"
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#ifdef __powerpc64__
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"lfd 13,8b@toc(2)\n\t"
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#else
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"mflr 11\n\t"
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"bcl 20,31,1f\n"
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"1:" "mflr 9\n\t"
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"addis 9,9,8b-1b@ha\n\t"
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"lfs 13,8b-1b@l(9)\n\t"
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"mtlr 11\n\t"
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#endif
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"fabs 0,1\n\t"
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"fsub 12,13,13\n\t"
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"fcmpu 7,0,13\n\t"
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"fcmpu 6,1,12\n\t"
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"bnllr- 7\n\t"
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"mtfsfi 7,2\n\t"
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"ble- 6,2f\n\t"
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"fadd 1,1,13\n\t"
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"fsub 1,1,13\n\t"
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"fabs 1,1\n\t"
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"mtfsf 0x01,11\n\t"
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"blr\n"
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"2:" "bge- 6,3f\n\t"
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"fsub 1,1,13\n\t"
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"fadd 1,1,13\n\t"
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"fnabs 1,1\n"
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"3:" "mtfsf 0x01,11\n\t"
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"blr\n\t"
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"# friz == trunc\n"
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"friz:" "mffs 11\n\t"
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#ifdef __powerpc64__
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"lfd 13,8b@toc(2)\n\t"
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#else
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"mflr 11\n\t"
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"bcl 20,31,1f\n"
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"1:" "mflr 9\n\t"
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"addis 9,9,8b-1b@ha\n\t"
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"lfs 13,8b-1b@l(9)\n\t"
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"mtlr 11\n\t"
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#endif
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"fabs 0,1\n\t"
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"fsub 12,13,13\n\t"
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"fcmpu 7,0,13\n\t"
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"fcmpu 6,1,12\n\t"
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"bnllr- 7\n\t"
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"mtfsfi 7,1\n\t"
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"ble- 6,2f\n\t"
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"fadd 1,1,13\n\t"
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"fsub 1,1,13\n\t"
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"fabs 1,1\n\t"
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"mtfsf 0x01,11\n\t"
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"blr\n"
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"2:" "bge- 6,3f\n\t"
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"fsub 1,1,13\n\t"
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"fadd 1,1,13\n\t"
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"fnabs 1,1\n"
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"3:" "mtfsf 0x01,11\n\t"
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"blr\n\t"
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"# frin == round\n"
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"frin:" "mffs 11\n\t"
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#ifdef __powerpc64__
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"lfd 13,8b@toc(2)\n\t"
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#else
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"mflr 11\n\t"
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"bcl 20,31,1f\n"
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"1:" "mflr 9\n\t"
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"addis 9,9,8b-1b@ha\n\t"
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"addi 9,9,8b-1b@l\n\t"
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"mtlr 11\n\t"
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"lfs 13,0(9)\n\t"
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#endif
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"fabs 0,1\n\t"
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"fsub 12,13,13\n\t"
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"fcmpu 7,0,13\n\t"
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"fcmpu 6,1,12\n\t"
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"bnllr- 7\n\t"
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"mtfsfi 7,1\n\t"
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#ifdef __powerpc64__
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"lfd 10,9b@toc(2)\n\t"
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#else
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"lfs 10,9b-8b(9)\n\t"
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#endif
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"ble- 6,2f\n\t"
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"fadd 1,1,10\n\t"
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"fadd 1,1,13\n\t"
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"fsub 1,1,13\n\t"
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"fabs 1,1\n\t"
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"mtfsf 0x01,11\n\t"
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"blr\n"
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"2:" "fsub 9,1,10\n\t"
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"bge- 6,3f\n\t"
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"fsub 1,9,13\n\t"
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"fadd 1,1,13\n\t"
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"fnabs 1,1\n"
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"3:" "mtfsf 0x01,11\n\t"
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"blr\n\t"
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"# frim == floor\n"
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"frim:" "mffs 11\n\t"
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#ifdef __powerpc64__
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"lfd 13,8b@toc(2)\n\t"
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#else
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"mflr 11\n\t"
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"bcl 20,31,1f\n"
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"1:" "mflr 9\n\t"
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"addis 9,9,8b-1b@ha\n\t"
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"lfs 13,8b-1b@l(9)\n\t"
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"mtlr 11\n\t"
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#endif
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"fabs 0,1\n\t"
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"fsub 12,13,13\n\t"
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"fcmpu 7,0,13\n\t"
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"fcmpu 6,1,12\n\t"
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"bnllr- 7\n\t"
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"mtfsfi 7,3\n\t"
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"ble- 6,2f\n\t"
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"fadd 1,1,13\n\t"
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"fsub 1,1,13\n\t"
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"fabs 1,1\n\t"
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"mtfsf 0x01,11\n\t"
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"blr\n"
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"2:" "bge- 6,3f\n\t"
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"fsub 1,1,13\n\t"
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"fadd 1,1,13\n\t"
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"fnabs 1,1\n"
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"3:" "mtfsf 0x01,11\n\t"
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"blr\n");
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#ifdef __powerpc64__
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#define m1 0x5555555555555555L
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#define m2 0x3333333333333333L
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#define m3 0x0f0f0f0f0f0f0f0fL
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#else
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#define m1 0x55555555
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#define m2 0x33333333
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#define m3 0x0f0f0f0f
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#endif
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static inline unsigned long
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popcntb (unsigned long n)
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{
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n -= (n >> 1) & m1;
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n = (n & m2) + ((n >> 2) & m2);
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n = (n + (n >> 4)) & m3;
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return n;
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}
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static void
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catch_sigill (int signal, struct sigcontext *ctx)
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{
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unsigned int insn = *(unsigned int *) (ctx->regs->nip);
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#ifdef __powerpc64__
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if ((insn & 0xfc1f07ff) == 0x7c0005be) /* mftgpr */
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{
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unsigned long *regs = (unsigned long *) ctx->regs;
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unsigned fpr = (insn >> 11) & 0x1f;
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unsigned gpr = (insn >> 21) & 0x1f;
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regs[gpr] = regs[fpr + 0x30];
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ctx->regs->nip += 4;
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return;
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}
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if ((insn & 0xfc1f07ff) == 0x7c0004be) /*mffgpr */
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{
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unsigned long *regs = (unsigned long *) ctx->regs;
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unsigned fpr = (insn >> 21) & 0x1f;
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unsigned gpr = (insn >> 11) & 0x1f;
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regs[fpr + 0x30] = regs[gpr];
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ctx->regs->nip += 4;
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return;
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}
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#endif
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if ((insn & 0xfc1f073f) == 0xfc000310) /* fri[pznm] */
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{
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#ifdef __powerpc64__
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double *regs = (double *) (((char *) ctx->regs) + 0x30 * 8);
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unsigned int *fpscr = (unsigned int *) (((char *) ctx->regs) + 0x50 * 8 + 4);
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#else
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double *regs = (double *) (((char *) ctx->regs) + 0x30 * 4);
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unsigned int *fpscr = (unsigned int *) (((char *) ctx->regs) + 0x30 * 4 + 0x20 * 8 + 4);
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#endif
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unsigned dest = (insn >> 21) & 0x1f;
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unsigned src = (insn >> 11) & 0x1f;
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switch (insn & 0xc0)
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{
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case 0:
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regs[dest] = frin (regs[src]);
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break;
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case 0x40:
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regs[dest] = friz (regs[src]);
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break;
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case 0x80:
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regs[dest] = frip (regs[src]);
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break;
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case 0xc0:
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regs[dest] = frim (regs[src]);
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break;
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}
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/* Update raised exceptions. */
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union { unsigned int i[2]; double d; } u;
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asm volatile ("mffs %0" : "=f" (u.d));
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u.i[1] &= 0xfffe0000; /* Is this correct? */
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*fpscr |= u.i[1];
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ctx->regs->nip += 4;
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return;
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}
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if ((insn & 0xfc00ffff) == 0x7c0000f4) /* popcntb */
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{
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unsigned long *regs = (unsigned long *) ctx->regs;
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unsigned dest = (insn >> 16) & 0x1f;
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unsigned src = (insn >> 21) & 0x1f;
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unsigned long res = 0;
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int i;
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regs[dest] = popcntb (regs[src]);
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ctx->regs->nip += 4;
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return;
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}
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struct sigaction sa;
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sa.sa_handler = SIG_DFL;
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sigemptyset (&sa.sa_mask);
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sa.sa_flags = 0;
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sigaction (signal, &sa, NULL);
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raise (signal);
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}
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static void
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__attribute__ ((constructor))
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install_handler (void)
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{
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struct sigaction sa;
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sa.sa_handler = (void *) catch_sigill;
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sigemptyset (&sa.sa_mask);
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sa.sa_flags = SA_RESTART;
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sigaction (SIGILL, &sa, NULL);
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}
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