94 lines
3.9 KiB
Diff
94 lines
3.9 KiB
Diff
From 2d8ef784bd6a784496a6fd460de6b6f57c70a501 Mon Sep 17 00:00:00 2001
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From: Aurelien Jarno <aurelien@aurel32.net>
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Date: Mon, 3 Oct 2022 23:46:11 +0200
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Subject: [PATCH 56/81] x86-64: Require BMI1/BMI2 for AVX2 strrchr and wcsrchr
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implementations
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The AVX2 strrchr and wcsrchr implementation uses the 'blsmsk'
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instruction which belongs to the BMI1 CPU feature and the 'shrx'
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instruction, which belongs to the BMI2 CPU feature.
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Fixes: df7e295d18ff ("x86: Optimize {str|wcs}rchr-avx2")
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Partially resolves: BZ #29611
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Reviewed-by: Noah Goldstein <goldstein.w.n@gmail.com>
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(cherry picked from commit 7e8283170c5d6805b609a040801d819e362a6292)
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---
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sysdeps/x86/isa-level.h | 1 +
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sysdeps/x86_64/multiarch/ifunc-avx2.h | 1 +
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sysdeps/x86_64/multiarch/ifunc-impl-list.c | 17 ++++++++++++++---
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3 files changed, 16 insertions(+), 3 deletions(-)
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diff --git a/sysdeps/x86/isa-level.h b/sysdeps/x86/isa-level.h
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index bbb90f5c5e..06f6c9663e 100644
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--- a/sysdeps/x86/isa-level.h
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+++ b/sysdeps/x86/isa-level.h
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@@ -79,6 +79,7 @@
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/* ISA level >= 3 guaranteed includes. */
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#define AVX_X86_ISA_LEVEL 3
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#define AVX2_X86_ISA_LEVEL 3
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+#define BMI1_X86_ISA_LEVEL 3
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#define BMI2_X86_ISA_LEVEL 3
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#define LZCNT_X86_ISA_LEVEL 3
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#define MOVBE_X86_ISA_LEVEL 3
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diff --git a/sysdeps/x86_64/multiarch/ifunc-avx2.h b/sysdeps/x86_64/multiarch/ifunc-avx2.h
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index f1741083fd..f2f5e8a211 100644
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--- a/sysdeps/x86_64/multiarch/ifunc-avx2.h
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+++ b/sysdeps/x86_64/multiarch/ifunc-avx2.h
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@@ -36,6 +36,7 @@ IFUNC_SELECTOR (void)
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const struct cpu_features *cpu_features = __get_cpu_features ();
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if (X86_ISA_CPU_FEATURE_USABLE_P (cpu_features, AVX2)
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+ && X86_ISA_CPU_FEATURE_USABLE_P (cpu_features, BMI1)
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&& X86_ISA_CPU_FEATURE_USABLE_P (cpu_features, BMI2)
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&& X86_ISA_CPU_FEATURE_USABLE_P (cpu_features, LZCNT)
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&& X86_ISA_CPU_FEATURES_ARCH_P (cpu_features,
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diff --git a/sysdeps/x86_64/multiarch/ifunc-impl-list.c b/sysdeps/x86_64/multiarch/ifunc-impl-list.c
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index ec1c5b55fb..00a91123d3 100644
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--- a/sysdeps/x86_64/multiarch/ifunc-impl-list.c
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+++ b/sysdeps/x86_64/multiarch/ifunc-impl-list.c
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@@ -578,13 +578,19 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array,
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IFUNC_IMPL (i, name, strrchr,
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X86_IFUNC_IMPL_ADD_V4 (array, i, strrchr,
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(CPU_FEATURE_USABLE (AVX512VL)
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- && CPU_FEATURE_USABLE (AVX512BW)),
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+ && CPU_FEATURE_USABLE (AVX512BW)
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+ && CPU_FEATURE_USABLE (BMI1)
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+ && CPU_FEATURE_USABLE (BMI2)),
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__strrchr_evex)
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X86_IFUNC_IMPL_ADD_V3 (array, i, strrchr,
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- CPU_FEATURE_USABLE (AVX2),
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+ (CPU_FEATURE_USABLE (AVX2)
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+ && CPU_FEATURE_USABLE (BMI1)
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+ && CPU_FEATURE_USABLE (BMI2)),
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__strrchr_avx2)
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X86_IFUNC_IMPL_ADD_V3 (array, i, strrchr,
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(CPU_FEATURE_USABLE (AVX2)
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+ && CPU_FEATURE_USABLE (BMI1)
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+ && CPU_FEATURE_USABLE (BMI2)
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&& CPU_FEATURE_USABLE (RTM)),
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__strrchr_avx2_rtm)
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/* ISA V2 wrapper for SSE2 implementation because the SSE2
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@@ -797,13 +803,18 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array,
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X86_IFUNC_IMPL_ADD_V4 (array, i, wcsrchr,
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(CPU_FEATURE_USABLE (AVX512VL)
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&& CPU_FEATURE_USABLE (AVX512BW)
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+ && CPU_FEATURE_USABLE (BMI1)
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&& CPU_FEATURE_USABLE (BMI2)),
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__wcsrchr_evex)
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X86_IFUNC_IMPL_ADD_V3 (array, i, wcsrchr,
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- CPU_FEATURE_USABLE (AVX2),
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+ (CPU_FEATURE_USABLE (AVX2)
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+ && CPU_FEATURE_USABLE (BMI1)
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+ && CPU_FEATURE_USABLE (BMI2)),
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__wcsrchr_avx2)
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X86_IFUNC_IMPL_ADD_V3 (array, i, wcsrchr,
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(CPU_FEATURE_USABLE (AVX2)
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+ && CPU_FEATURE_USABLE (BMI1)
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+ && CPU_FEATURE_USABLE (BMI2)
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&& CPU_FEATURE_USABLE (RTM)),
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__wcsrchr_avx2_rtm)
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/* ISA V2 wrapper for SSE2 implementation because the SSE2
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--
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2.19.1.6.gb485710b
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