74 lines
2.9 KiB
Diff
74 lines
2.9 KiB
Diff
From 923c3f3c373f499e62160e00831dda576443317b Mon Sep 17 00:00:00 2001
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From: Aurelien Jarno <aurelien@aurel32.net>
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Date: Mon, 3 Oct 2022 23:46:11 +0200
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Subject: [PATCH 55/81] x86-64: Require BMI2 and LZCNT for AVX2 memrchr
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implementation
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The AVX2 memrchr implementation uses the 'shlxl' instruction, which
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belongs to the BMI2 CPU feature and uses the 'lzcnt' instruction, which
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belongs to the LZCNT CPU feature.
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Fixes: af5306a735eb ("x86: Optimize memrchr-avx2.S")
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Partially resolves: BZ #29611
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Reviewed-by: Noah Goldstein <goldstein.w.n@gmail.com>
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(cherry picked from commit 3c0c78afabfed4b6fc161c159e628fbf14ff370b)
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---
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sysdeps/x86/isa-level.h | 1 +
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sysdeps/x86_64/multiarch/ifunc-avx2.h | 1 +
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sysdeps/x86_64/multiarch/ifunc-impl-list.c | 10 ++++++++--
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3 files changed, 10 insertions(+), 2 deletions(-)
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diff --git a/sysdeps/x86/isa-level.h b/sysdeps/x86/isa-level.h
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index 3c4480aba7..bbb90f5c5e 100644
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--- a/sysdeps/x86/isa-level.h
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+++ b/sysdeps/x86/isa-level.h
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@@ -80,6 +80,7 @@
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#define AVX_X86_ISA_LEVEL 3
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#define AVX2_X86_ISA_LEVEL 3
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#define BMI2_X86_ISA_LEVEL 3
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+#define LZCNT_X86_ISA_LEVEL 3
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#define MOVBE_X86_ISA_LEVEL 3
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/* ISA level >= 2 guaranteed includes. */
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diff --git a/sysdeps/x86_64/multiarch/ifunc-avx2.h b/sysdeps/x86_64/multiarch/ifunc-avx2.h
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index a57a9952f3..f1741083fd 100644
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--- a/sysdeps/x86_64/multiarch/ifunc-avx2.h
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+++ b/sysdeps/x86_64/multiarch/ifunc-avx2.h
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@@ -37,6 +37,7 @@ IFUNC_SELECTOR (void)
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if (X86_ISA_CPU_FEATURE_USABLE_P (cpu_features, AVX2)
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&& X86_ISA_CPU_FEATURE_USABLE_P (cpu_features, BMI2)
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+ && X86_ISA_CPU_FEATURE_USABLE_P (cpu_features, LZCNT)
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&& X86_ISA_CPU_FEATURES_ARCH_P (cpu_features,
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AVX_Fast_Unaligned_Load, ))
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{
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diff --git a/sysdeps/x86_64/multiarch/ifunc-impl-list.c b/sysdeps/x86_64/multiarch/ifunc-impl-list.c
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index 7c84963d92..ec1c5b55fb 100644
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--- a/sysdeps/x86_64/multiarch/ifunc-impl-list.c
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+++ b/sysdeps/x86_64/multiarch/ifunc-impl-list.c
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@@ -209,13 +209,19 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array,
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IFUNC_IMPL (i, name, memrchr,
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X86_IFUNC_IMPL_ADD_V4 (array, i, memrchr,
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(CPU_FEATURE_USABLE (AVX512VL)
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- && CPU_FEATURE_USABLE (AVX512BW)),
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+ && CPU_FEATURE_USABLE (AVX512BW)
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+ && CPU_FEATURE_USABLE (BMI2)
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+ && CPU_FEATURE_USABLE (LZCNT)),
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__memrchr_evex)
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X86_IFUNC_IMPL_ADD_V3 (array, i, memrchr,
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- CPU_FEATURE_USABLE (AVX2),
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+ (CPU_FEATURE_USABLE (AVX2)
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+ && CPU_FEATURE_USABLE (BMI2)
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+ && CPU_FEATURE_USABLE (LZCNT)),
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__memrchr_avx2)
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X86_IFUNC_IMPL_ADD_V3 (array, i, memrchr,
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(CPU_FEATURE_USABLE (AVX2)
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+ && CPU_FEATURE_USABLE (BMI2)
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+ && CPU_FEATURE_USABLE (LZCNT)
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&& CPU_FEATURE_USABLE (RTM)),
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__memrchr_avx2_rtm)
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/* ISA V2 wrapper for SSE2 implementation because the SSE2
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--
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2.19.1.6.gb485710b
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